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GHC 9.10.3 · lts/ghc-9.10.x · c74966e · 2026-09-27

Moduleghc-9.10.3GHC2021

GHC.CmmToAsm.AArch64.Instr

  • 7 types
  • 97 values
  • Packageghc-9.10.3
  • Exports104
  • LanguageGHC2021
  • LicenceBSD-3-Clause
  • SourceInstr.hs
valuestackAlign :: Int
#

The number of bytes that the stack pointer should be aligned to.

valuecallerSavedRegisters :: [Reg]
#

0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 | | 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 42 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | |== General Purpose registers ==================================================================================================================================| | argument passing ------------- | IR | tmp registers -------- | IP0| IP1| PL | callee saved ------------ | FP | LR | SP | | free registers -------------------------------------------------------------------- | BR | Sp | Hp | R1 | R2 | R3 | R4 | R5 | R6 | SL | -- | -- | -- | |== SIMD/FP Registers ==========================================================================================================================================| | argument passing ------------- | callee saved (lower 64 bits) --- | caller saved ---------------------- | | free registers ------------- | F1 | F2 | F3 | F4 | D1 | D2 | D3 | D4 | free registers ----------------------------------------------------- | --------------------------------------------------------------------------------------------------------------------------------------------------------------- IR: Indirect result location register, IP: Intra-procedure register, PL: Platform register, FP: Frame pointer, LR: Link register, SP: Stack pointer BR: Base, SL: SpLim

TODO: The zero register is currently mapped to -1 but should get it's own separate number.

valueisJumpishInstr :: Instr -> Bool
#

Checks whether this instruction is a jump/branch instruction. One that can change the flow of control in a way that the register allocator needs to worry about.

valuejumpDestsOfInstr :: Instr -> [BlockId]
#

Checks whether this instruction is a jump/branch instruction. One that can change the flow of control in a way that the register allocator needs to worry about.

datadata Instr
#

Constructors

Instances1Instruction
  • Instruction InstrDefined in ghc-9.10.3 · GHC.CmmToAsm.AArch64 · orphan

    Instruction instance for aarch64

Orphan instances

1 instance
  • Outputable RegUsage

    Get the registers that are being used by this instruction. regUsage doesn't need to do any trickery for jumps and such. Just state precisely the regs read and written by that insn. The consequences of control flow transfers, as far as register allocation goes, are taken care of by the register allocator.

    RegUsage = RU [regs] [regs]