LR and FP (8 byte each) are the prologue of each stack frame
Moduleghc-9.10.3GHC2021
GHC.CmmToAsm.AArch64.Instr
- 7 types
- 97 values
- Packageghc-9.10.3
- Exports104
- LanguageGHC2021
- LicenceBSD-3-Clause
- SourceInstr.hs
All registers are 8 byte wide.
The number of bytes that the stack pointer should be aligned to.
The number of spill slots available without allocating more.
Convert a spill slot number to a *byte* offset, with no sign.
0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 | 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 | 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 |
| 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 | 40 | 41 | 42 | 42 | 44 | 45 | 46 | 47 | 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 | 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 |
|== General Purpose registers ==================================================================================================================================|
| argument passing ------------- | IR | tmp registers -------- | IP0| IP1| PL | callee saved ------------ | FP | LR | SP |
| free registers -------------------------------------------------------------------- | BR | Sp | Hp | R1 | R2 | R3 | R4 | R5 | R6 | SL | -- | -- | -- |
|== SIMD/FP Registers ==========================================================================================================================================|
| argument passing ------------- | callee saved (lower 64 bits) --- | caller saved ---------------------- |
| free registers ------------- | F1 | F2 | F3 | F4 | D1 | D2 | D3 | D4 | free registers ----------------------------------------------------- |
---------------------------------------------------------------------------------------------------------------------------------------------------------------
IR: Indirect result location register, IP: Intra-procedure register, PL: Platform register, FP: Frame pointer, LR: Link register, SP: Stack pointer
BR: Base, SL: SpLim
TODO: The zero register is currently mapped to -1 but should get it's own separate number.
Apply a given mapping to all the register references in this instruction.
Checks whether this instruction is a jump/branch instruction. One that can change the flow of control in a way that the register allocator needs to worry about.
Checks whether this instruction is a jump/branch instruction. One that can change the flow of control in a way that the register allocator needs to worry about.
Change the destination of this jump instruction. Used in the linear allocator when adding fixup blocks for join points.
An instruction to spill a register into a spill slot.
See if this instruction is telling us the current C stack delta
Copy the value in a register to another one. Must work for all register classes.
Take the source and destination from this reg -> reg move instruction or Nothing if it's not one
Make an unconditional jump instruction.
Constructors
COMMENT SDocMULTILINE_COMMENT SDocANN SDoc InstrLOCATION Int Int Int StringNEWBLOCK BlockIdDELTA IntSXTB Operand OperandUXTB Operand OperandSXTH Operand OperandUXTH Operand OperandPUSH_STACK_FRAMESXTW Operand Operand | SXTX Operand Operand
POP_STACK_FRAMEADD Operand Operand OperandADC Operand Operand Operand -- rd = rn + rm + C | ADCS ...
CMP Operand OperandADDS Operand Operand Operand -- rd = rn + rm | ADR ... | ADRP ...
CMN Operand OperandMSUB Operand Operand Operand OperandMADD ... | MNEG ...
MUL Operand Operand OperandNEG Operand OperandSDIV Operand Operand OperandNEGS ... | NGC ... | NGCS ... | SBC ... | SBCS ...
SMULH Operand Operand OperandSMADDL ... | SMNEGL ... | SMSUBL ...
SMULL Operand Operand OperandSUB Operand Operand OperandUDIV Operand Operand OperandSUBS ...
UMULH Operand Operand OperandUMADDL ... -- Xd = Xa + Wn × Wm | UMNEGL ... -- Xd = - Wn × Wm | UMSUBL ... -- Xd = Xa - Wn × Wm
UMULL Operand Operand OperandSBFM Operand Operand Operand OperandUBFM Operand Operand Operand OperandSBFX Operand Operand Operand OperandUBFX Operand Operand Operand OperandCLZ Operand OperandRBIT Operand OperandREV Operand OperandREV16 Operand OperandAND Operand Operand OperandREV32 Operand Operand -- rd = reverseBytes32(rn) - 64bit operands only! -- 0xAABBCCDD_EEFFGGHH -> 0XDDCCBBAA_HHGGFFEE
ASR Operand Operand OperandEOR Operand Operand OperandLSL Operand Operand OperandLSR Operand Operand OperandMOV Operand OperandMOVK Operand OperandMOVZ Operand OperandMOVN Operand Operand
MVN Operand OperandORR Operand Operand OperandSTR Format Operand OperandSTLR Format Operand OperandLDR Format Operand OperandLDAR Format Operand OperandCSET Operand CondCBZ Operand TargetCBNZ Operand TargetJ TargetB TargetBL Target [Reg]BCOND Cond TargetDMBISHFCVT Operand OperandSCVTF Operand OperandFCVTZS Operand OperandFABS Operand OperandFSQRT Operand OperandFMA FMASign Operand Operand Operand OperandFloating-point fused multiply-add instructions
fmadd : d = r1 * r2 + r3
fnmsub: d = r1 * r2 - r3
fmsub : d = - r1 * r2 + r3
fnmadd: d = - r1 * r2 - r3
Instances1Instruction
Instruction InstrDefined in ghc-9.10.3 · GHC.CmmToAsm.AArch64 · orphanInstruction instance for aarch64
Orphan instances
1 instanceOutputable RegUsageGet the registers that are being used by this instruction. regUsage doesn't need to do any trickery for jumps and such. Just state precisely the regs read and written by that insn. The consequences of control flow transfers, as far as register allocation goes, are taken care of by the register allocator.